This directory contains the source content used to create the following six tutorials that are designed to run on the Terasic DE10-Nano development kit by Terasic Technologies Inc. The PDF files for these tutorials can be downloaded from the GitHub* release download page here.
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How to Program Your First FPGA Device
The Qsys tool allows a designer to choose the components that are desired in the system by selecting these com- ponents in a graphical user interface. It then automatically generates the hardware system that connects all of the. The components in the memory tester system are grouped into a single Qsys system with three major design functions. The design hierarchy allows you to instantiate the data pattern generator and data pattern checker components into separate systems. You can then add the memory tester system with the memory master and controller components.
This tutorial demonstrates how to create the hardware equivalent of 'Hello World': a blinking LED. This is a simple exercise to get you started using the Intel® Quartus® software for FPGA development.
You'll learn to compile Verilog code, make pin assignments, create timing constraints, and then program the FPGA to blink one of the eight green user LEDs on the board. You'll use a 50 MHz clock input (from the on-board oscillator) to drive a counter, and assign an LED to one of the counter output bits.
Download the tutorial PDF file writeup_MyFirstFPGA.pdfhere.
My First Qsys System
This tutorial demonstrates how to use the Qsys system integration tool to easily create an FPGA design using IP available in the Intel® Quartus® software IP catalog. Qsys speeds embedded system design by standardizing the interconnect between IP blocks and allowing users to create their own IP blocks for reuse in their systems.
Download the tutorial PDF file writeup_MyFirstQsysSystem.pdfhere.
Interacting with FPGA Designs using System Console
This tutorial demonstrates how to use the System Console debugging tool to program a compiled FPGA design into an FPGA device, then access the hardware modules instantiated in that FPGA design. This System Console tutorial is based on the FPGA design created in the 'My First Qsys System' tutorial.
In this tutorial we will demonstrate how you can interact with the Qsys system through a JTAG cable connected to the FPGA that can send read and write transactions through the JTAG master in the Qsys system to interact with the slave peripherals it is connected to.
Download the tutorial PDF file writeup_InteractSystemConsole.pdfhere.
My First HPS System
This tutorial demonstrates how to instantiate and configure a Hard Processor System (HPS) component into a Qsys system. Unlike other components in the prior 'My First Qsys System' tutorial, the HPS component does not define any soft logic to be configured in the FPGA, rather, it allows the designer to configure the interfaces between the existing processor hardware on the Intel® SoC FPGA chip. Configuring an entire processor system is a necessarily detailed process, but the level of customization available is precisely the advantage an Intel® SoC FPGA provides. This tutorial shows as closely as possible how to set up the HPS in a similar manner to the design that shipped with the Terasic DE10-Nano board, and integrate it with the existing Qsys system from the preceding 'My First Qsys System' tutorial. This will allow us to integrate this example onto the existing SD card image that ships with the Terasic DE10-Nano board.
Download the tutorial PDF file writeup_MyFirstHPSSystem.pdfhere.
Interacting with FPGA Designs using U-Boot
This tutorial demonstrates how to use the U-Boot boot loader to program a compiled FPGA design into an Intel® SoC FPGA device, then interact with the hardware modules instantiated in that FPGA design from the HPS processor using U-Boot. This U-Boot tutorial is based on the FPGA design created in a prior tutorial 'My First HPS System'.
In this tutorial we will demonstrate how you can interact with the Qsys system in the FPGA through the HPS-to-FPGA bridges provided on the HPS core, reading and writing to the slave peripherals they are connected to. Both U-Boot console commands and a U-Boot standalone application are used to interact with the soft IP peripherals residing in the FPGA fabric.
Download the tutorial PDF file writeup_u-boot.pdfhere.
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Interacting with FPGA Designs using Linux*
This tutorial demonstrates how to use various Linux* capabilities to interact with the hardware modules instantiated in an FPGA design from the HPS processor. This Linux tutorial is based on the FPGA design created in a prior tutorial 'My First HPS System'.
In this tutorial we will demonstrate how you can interact with the Qsys system in the FPGA through the HPS-to-FPGA bridges provided on the HPS core, reading and writing to the slave peripherals they are connected to. We demonstrate the devmem and devmem2 programs that can peek and poke at the FPGA peripherals. We also demonstrate how to build a Linux application to interact with those same soft IP peripherals. Finally we demonstrate how to use a number of sysfs capabilities provided by existing device drivers for the FPGA based peripherals which we will enable with a device tree overlay.
Download the tutorial PDF file writeup_linux.pdfhere.
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